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| a FEATURES Ultralow Offset Voltage: TA = +25 C: 10 V max -55 C TA +125 C: 20 V max Outstanding Offset Voltage Drift: 0.1 V/ C max Excellent Open-Loop Gain and Gain Linearity: 12 V/ V typ CMRR: 130 dB min PSRR: 120 dB min Low Supply Current: 2.0 mA max Fits Industry Standard Precision Op Amp Sockets (OP07/OP77) Ultraprecision Operational Amplifier OP177 PIN CONNECTIONS Epoxy Mini-DIP OP177BRC/883 (P Suffix) LCC (RC Suffix) 8-Pin Hermetic DIP (Z-Suffix) 8-Pin SO (S-Suffix) NC = NO CONNECT NC = NO CONNECT GENERAL DESCRIPTION The OP177 features the highest precision performance of any op amp currently available. Offset voltage of the OP177 is only 10 V max at room temperature and 20 V max over the full military temperature range of -55C to +125C. The ultralow VOS of the OP177, combines with its exceptional offset voltage drift (TCVOS) of 0.1 V/C max, to eliminate the need for external VOS adjustment and increases system accuracy over temperature. The OP177's open-loop gain of 12 V/V is maintained over the full 10 V output range. CMRR of 130 dB min, PSRR of 120 dB min, and maximum supply current of 2 mA are just a few examples of the excellent performance of this operational amplifier. The OP177's combination of outstanding specifications insure accurate performance in high closed-loop gain applications. This low noise bipolar input op amp is also a cost effective alternative to chopper-stabilized amplifiers. The OP177 provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. The OP177 is offered in both the -55C to +125C military, and the -40C to +85C extended industrial temperature ranges. This product is available in 8-pin ceramic and epoxy DIPs, as well as the space saving 8-pin Small-Outline (SO) and the Leadless Chip Carrier (LCC) packages. Figure 1. Simplified Schematic REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 OP177-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = S 15 V, TA = +25 C, unless otherwise noted) Min OP177A Typ Max 4 0.2 0.3 -0.2 118 3 45 200 14 140 125 12000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 1.6 10 1.0 1.5 150 8 Min OP177B Typ 10 0.2 0.3 -0.2 Max 25 1.5 2.0 150 8 Units V V/Mo nA nA nV rms pA rms M G V dB dB V/mV V V V V/s MHz mW mW mA Parameter Input Offset Voltage Long-Term Input Offset Voltage Stability Input Offset Current Input Bias Current Input Noise Voltage Input Noise Current Input Resistance Differential-Mode Input Resistance Common-Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing Symbol VOS VOS/Time IOS IB en in RIN RINCM IVR CMRR PSRR AVO VO Conditions (Note 1) fo = 1 Hz to 100 Hz2 fo = 1 Hz to 100 Hz2 (Note 3) (Note 4) VCM = 13 V VS = 3 V to 18 V RL 2 k, VO = 10 V5 RL 10 k RL 2 k RL 1 k RL 2 k2 AVCL = +12 VS = 15 V, No Load VS = 3 V, No Load VS = 15 V, No Load Rp = 20 k 26 13 130 120 5000 13.5 12.5 12.0 0.1 0.4 Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Supply Current Offset Adjustment Range SR BW RO PD ISY 3 60 4.5 2.0 118 3 26 45 200 13 14 130 140 115 125 5000 12000 13.5 14.0 12.5 13.0 12.0 12.5 0.1 0.3 0.4 0.6 60 50 60 3.5 4.5 1.6 2.0 3 mV NOTES 1 Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V OS during the first 30 operating days are typically less than 2.0 V. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To insure high open-loop gain throughout the 10 V output range, A VO is tested at -10 V VO 0 V, 0 V VO +10 V, and -10 V VO +10 V. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS (@ V Parameter Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Average Input Offset Current Drift Input Bias Current Average Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Power Consumption Supply Current Symbol VOS TCVOS IOS TCIOS IB TCIB IVR CMRR PSRR AVO VO PD ISY S = 15 V, -55C TA +125 C, unless otherwise noted) Min OP177A Typ Max 10 0.03 0.5 1.5 2.4 8 13.5 140 125 6000 13.0 60 2.0 20 0.1 1.5 25 4 25 Min OP177B Typ 25 0.1 0.5 1.5 2.4 8 13.5 140 120 6000 13.0 60 2.0 Max 55 0.3 2.0 25 4 25 Units V V/C nA pA/C nA pA/C V dB dB V/mV V mW mA Conditions (Note 1) (Note 2) -0.2 (Note 2) (Note 3) VCM = 13 V VS = 3 V to 18 V RL 2 k, VO = 10 V4 RL 2 k VS = 15 V, No Load VS = 15 V, No Load 13 120 120 2000 12 -0.2 13 120 110 2000 12 75 2.5 75 2.5 NOTES 1 TCVOS is 100% tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To insure high open-loop gain throughout the 10 V output range, A VO is tested at -10 V VO 0 V, 0 V VO +10 V, and -10 V VO +10 V. Specifications subject to change without notice. -2- REV. B ELECTRICAL CHARACTERISTICS Parameter Input Offset Voltage Long-Term Input Offset Voltage Stability Input Offset Current Input Bias Current Input Noise Voltage Input Noise Current Input Resistance Differential-Mode Input Resistance Common-Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing Symbol VOS Conditions (@ VS = Min 15 V, TA = +25 C, unless otherwise noted) OP177E Typ Max 4 0.2 0.3 1.0 118 3 45 200 14 140 125 12000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 1.6 3 10 Min OP177F Typ 10 0.3 0.3 1.2 118 3 45 200 14 140 125 12000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 1.6 3 Max 25 Min OP177G Typ 20 0.4 0.3 1.2 118 3 45 200 14 140 120 6000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 1.6 3 Max 60 OP177 Units V V/Mo nA nA nV rms pA rms M G V dB dB V/mV V V V V/s MHz mW mW mA mV VOS/Time (Note 1) IOS IB fo = 1 Hz to 100 Hz2 en in fo = 1 Hz to 100 Hz2 RIN RINCM IVR CMRR PSRR AVO VO (Note 3) -0.2 1.0 1.5 150 8 -0.2 1.5 2.0 150 8 -0.2 2.8 2.8 150 8 26 13 130 120 5000 13.5 12.5 12.0 0.1 0.4 26 13 130 115 5000 13.5 12.5 12.0 0.1 0.4 18.5 13 115 110 2000 13.5 12.5 12.0 0.1 0.4 (Note 4) VCM = 13 V VS = 3 V to 18 V RL 2 k, VO = 10 V5 RL 10 k RL 2 k RL 1 k RL 2 k2 AVCL = +12 VS = 15 V, No Load VS = 3 V, No Load VS = 15 V, No Load RP = 20 k Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Supply Current Offset Adjustment Range SR BW RO PD ISY 60 4.5 2.0 60 4.5 2.0 60 4.5 2.0 NOTES 1 Long-Term Input Offset Voltage Stability refers to the averaged trend line of V OS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in V OS during the first 30 operating days are typically less than 2.0 V. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To insure high open-loop gain throughout the 10 V output range, A VO is tested at -10 V VO 0 V, 0 V VO +10 V, and -10 V VO +10 V. Specifications subject to change without notice. REV. B -3- OP177-SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Average Input Offset Current Drift Input Bias Current Average Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Power Consumption Supply Current Symbol VOS TCVOS IOS TCIOS IB TCIB IVR CMRR PSRR AVO VO PD ISY (Note 1) Conditions (@ VS = 15 V, -40C TA +85 C, unless otherwise noted) OP177E Typ Max 10 0.03 0.5 1.5 2.4 8 13.5 140 125 6000 13.0 60 2.0 20 0.1 1.5 25 4 25 Min OP177F Typ 15 0.1 0.5 1.5 2.4 8 13.5 140 120 6000 13.0 60 2.0 Max 40 0.3 2.2 40 4 40 13.0 110 106 1000 12.0 75 2.5 Min OP177G Typ 20 0.7 0.5 1.5 2.4 15 13.5 140 115 4000 13.0 60 2.0 Max 100 1.2 4.5 85 6.0 60 Units V V/C nA pA/C nA pA/C V dB dB V/mV V mW Min (Note 2) -0.2 (Note 2) (Note 3) VCM = 13 V VS = 3 V to 18 V RL 2 k, VO = 10 V4 RL 2 k VS = 15 V, No Load VS = 15 V, No Load 13 120 120 2000 12 -0.2 13 120 110 2000 12 75 2.5 75 2.5 mA NOTES 1 OP177E: TCVOS is 100% tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To insure high open-loop gain throughout the 10 V output range, A VO is tested at -10 V VO 0 V, 0 V VO +10 V, and -10 V VO +10 V. Specifications subject to change without notice. Figure 2. Typical Offset Voltage Test Circuit Figure 3. Optional Offset Nulling Circuit -4- REV. B OP177 Figure 4. Burn-In Circuit ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V Internal Power Dissipation1 . . . . . . . . . . . . . . . . . . . 500 mW Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 30 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range Z and RC Packages . . . . . . . . . . . . . . . . . -65C to +150C S, P Package . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range OP177A, OP177B . . . . . . . . . . . . . . . . . -55C to +125C OP177E, OP177F, OP177G . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering, 60 sec) . . . . . . +300C DICE Junction Temperature (TJ) . . . . . . . -65C to +150C Package Type 8-Pin Hermetic DIP (Z) 8-Pin Plastic DIP (P) 20-Contact LCC (RC) 8-Pin SO (S) JA 2 JC ORDERING GUIDE Model OP177AZ OP177BZ OP177EZ OP177FZ OP177GZ OP177FP OP177GP OP177BRC/883 OP177FS OP177GS Temperature Range -55C to +125C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C Package Description 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 8-Pin Plastic DIP 8-Pin Plastic DIP 20-Pin LCC 8-Pin SO 8-Pin SO Package Option Q-8 Q-8 Q-8 Q-8 Q-8 N-8 N-8 E-20A SO-8 SO-8 Units C/W C/W C/W C/W 148 103 98 158 16 43 38 43 NOTES 1 For supply voltages less than 22 V, the absolute maximum input voltage is equal to the supply voltage. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip, P-DIP, and LCC packages; JA is specified for device soldered to printed circuit board for SO package. REV. B -5- OP177-Typical Performance Characteristics Figure 5. Gain Linearity (Input Voltage vs. Output Voltage) Figure 6. Power Consumption vs. Power Supply Figure 7. Warm-Up VOS Drift (Normalized) Z Package Figure 8. Offset Voltage Change Due to Thermal Shock Figure 9. Open-Loop Gain vs. Temperature Figure 10. Open-Loop Gain vs. Power Supply Voltage Figure 11. Input Bias Current vs. Temperature Figure 12. Input Offset Current vs. Temperature Figure 13. Closed-Loop Response for Various Gain Configurations OP177 Figure 14. Open-Loop Frequency Response Figure 15. CMRR vs. Frequency Figure 16. PSRR vs. Frequency Figure 17. Total Input Noise Voltage vs. Frequency Figure 18. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency Indicated) Figure 19. Maximum Output Swing vs. Frequency Figure 20. Maximum Output Voltage vs. Load Resistance Figure 21. Output Short Circuit Current vs. Time REV. B -7- OP177 APPLICATIONS INFORMATION Gain Linearity THERMOCOUPLE AMPLIFIER WITH COLD-JUNCTION COMPENSATION The actual open-loop gain of most monolithic op amps varies at different output voltages. This nonlinearity causes errors in high closed-loop gain circuits. It is important to know that the manufacturer's AVO specification is only a part of the solution, since all automated testers use endpoint testing and, therefore, only show the average gain. For example, Figure 22 shows a typical precision op amp with a respectable open-loop gain of 650 V/mV. However, the gain is not constant through the output voltage range, causing nonlinear errors. An ideal op amp would show a horizontal scope trace. An example of a precision circuit is a thermocouple amplifier that must amplify very low level signals accurately without introducing linearity and offset errors to the circuit. In this circuit, an S-type thermocouple, which has a Seebeck coefficient of 10.3 V/C, produces 10.3 mV of output voltage at a temperature of 1,000C. The amplifier gain is set at 973.16. Thus, it will produce an output voltage of 10.024 V. Extended temperature ranges to beyond 1,500C can be accomplished by reducing the amplifier gain. The circuit uses a low-cost diode to sense the temperature at the terminating junctions and in turn compensates for any ambient temperature change. The OP177, with its high open-loop gain, plus low offset voltage and drift combines to yield a very precision temperature sensing circuit. Circuit values for other thermocouple types are shown in Table I. Table I. ThermoSeebeck couple Type Coefficient K J S 39.2 V/C 50.2 V/C 10.3 V/C R1 110 100 100 R2 5.76 k 4.02 k 20.5 k R7 R9 102 k 269 k 80.6 k 200 k 392 k 1.07 M Figure 22. Typical Precision Op Amp Figure 23. OP177's Output Gain Linearity Trace Figure 25. Thermocouple Amplifier with Cold Junction Compensation PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER The high gain, gain linearity, CMRR, and low TCVOS of the OP177 make it possible to obtain performance not previously available in single stage, very high-gain amplifier applications. See Figure 26. Figure 24. Open-Loop Gain Linearity Test Circuit For best CMR, Figure 23 shows the OP177's output gain linearity trace with its truly impressive average AVO of 12000 V/mV. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. PMI also performs additional testing to insure consistent high open-loop gain at various output voltages. Figure 24 is a simple open-loop gain test circuit for your own evaluation. R1 R3 must equal . In this example, with a R2 R4 10 mV differential signal, the maximum errors are as listed in Table II. OP177 ISOLATING LARGE CAPACITIVE LOADS The circuit in Figure 27 reduces maximum slew-rate but allows driving capacitive loads of any size without instability. Because the 100 resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high openloop gain of the OP177. Figure 26. Precision High Gain Differential Amplifier Table II. High Gain Differential Amp Performance Type Common-Mode Voltage Gain Linearity, Worst Case TCVOS TCIOS Amount 0.1%/V 0.02% 0.0003%/C 0.008%/C Figure 27. Isolating Capacitive Loads Figure 28. Bilateral Current Source Figure 29. Precision Absolute Value Amplifier OP177 BILATERAL CURRENT SOURCE PRECISION ABSOLUTE VALUE AMPLIFIER The current sources shown in Figure 28 will supply both positive and negative current into a grounded load. R4 R5 +1 R2 Note that ZO = R5+ R4 R3 - R1 R2 and that for ZO to be infinite, R5+ R4 R3 must = R2 R1 The high gain and low TCVOS assure accurate operation with inputs from microvolts to volts. In this circuit, the signal always appears as a common-mode signal to the op amps. The OP177E CMRR of 140 dB assures errors of less than 1 ppm. See Figure 29. Figure 30. Precision Positive Peak Detector PRECISION POSITIVE PEAK DETECTOR In Figure 30, the CH must be of polystyrene, Teflon*, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the OP41. PRECISION THRESHOLD DETECTOR/AMPLIFIER In Figure 32, when VIN < VTH, amplifier output swings negative, reverse biasing diode D1. VOUT = VTH if RL = . When VIN VTH, the loop closes, R VOUT =VTH + (VIN -VTH ) 1+ F RS CC is selected to smooth the response of the loop. *Teflon is a registered trademark of the Dupont Company. Figure 31. Precision Threshold Detector/Amplifier -10- REV. B OP177 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Cerdip (Q-8) 0.005 (0.13) MIN 0.055 (1.4) MAX 8 5 8-Pin SO (SO-08) 8 PIN 1 1 5 0.310 (7.87) 0.220 (5.59) 4 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80) PIN 1 1 4 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.100 0.070 (1.78) 0.014 (0.36) (2.54) 0.030 (0.76) BSC 0.0196 (0.50) x 45 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 15 0 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) SEATING PLANE 8-Pin Plastic DIP (N-8) 20-Pin LCC (E-20A) 0.200 (5.08) BSC 0.100 (2.54) BSC 3 4 1 8 PIN 1 1 5 0.280 (7.11) 0.240 (6.10) 4 0.358 (9.09) 0.342 (8.69) SQ 0.100 (2.54) 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) 0.075 (1.91) REF 19 18 20 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) TOP VIEW 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF BOTTOM VIEW 14 13 8 9 45 TYP 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) REV. B -11- -12- C2087-5-11/95 PRINTED IN U.S.A. |
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